Architecture of an efficient at-speed programmable memory built-in self test
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United States of America Patent
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Feb 13, 2007
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app pub date -
Jun 16, 2004
filing date -
Jun 16, 2004
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Abstract
A method of testing an embedded memory at speed within an integrated circuit which includes providing a memory built in self test sequencer module, providing a satellite engine module coupled to the memory built in self test sequencer module and applying a march test to the embedded memory via the satellite engine module based upon information stored within the instruction buffer. The satellite engine module includes an instruction buffer and a sequence generation engine.
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