Integrated circuit with improved interconnect structure and process for making same
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United States of America Patent
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Feb 20, 2007
Issued Date -
N/A
app pub date -
Jan 3, 2005
filing date -
May 3, 1999
priority date (Note) -
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Abstract
A semiconductor die and an associated low resistance interconnect located primarily on the bottom surface of such die is disclosed. This arrangement provides a flexible packaging structure permitting easy interconnected with other integrated circuits; in this manner, a number of such circuits can be stacked to create high circuit density multi-chip modules. A process for making the device is further disclosed. To preserve structural integrity of a wafer containing such die during manufacturing, a through-hole via formed as part of the interconnect is filled with an inert material during operations associated with subsequent active device formation on such die.
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