Apparatus and method for large hardware finite state machine with embedded equivalence classes

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United States of America Patent

PATENT NO 7180328
APP PUB NO 20050035784A1





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A programmable finite state machine (FSM) includes, in part, a first address calculation logic block, a first lookup table, a second address calculation logic block, and a second lookup table. The first address calculation logic block generates an address for the first lookup table based on the received input symbol and the current state. The data stored in first look-up table at the generated address is used by the second address calculation logic block to compute an address for the second lookup table. Data stored in the second lookup table is the next state to which the FSM transitions. The programmable FSMs uses redundant information of the transition table to compress these transitions and thus requires a smaller memory while maintaining a high data throughput. The data in the first and second lookup tables are coded and supplied by a compiler. The FSM operation may optionally be pipelined.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
Sensory Networks, Inc.PALO ALTO, CA5

International Classification(s)

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Inventor Name Address # of filed Patents Total Citations
Barrie, Robert Matthew Double Bay, AU 22 733
Flanagan, Michael Newtown, AU 18 305
Gould, Stephen Queens Park, AU 43 841
Peltzer, Ernest Eastwood, AU 4 76
Williams, Darren Newtown, AU 27 730

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