Systems and methods for minimizing harmonic interference
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United States of America Patent
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Feb 20, 2007
Issued Date -
N/A
app pub date -
Dec 6, 2005
filing date -
Oct 9, 2001
priority date (Note) -
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Abstract
Systems and methods are disclosed for minimizing nth-order harmonic associated with a square wave clock signal having a predetermined frequency and duty cycle. The system changes the duty cycle of the clock to eliminate or suppress the nth-order harmonic of the clock; and generates a low-interference clock having the changed duty cycle while keeping the predetermined frequency.
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