Processor isolation technique for integrated multi-processor systems
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United States of America Patent
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Feb 27, 2007
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N/A
app pub date -
Dec 10, 2003
filing date -
Nov 3, 1999
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Abstract
A processor isolation technique enhances debug capability in a multiprocessor circuit. A bypass register has a bit location which may indicate that a processor is to be bypassed. A code entry point is selected to permit a downstream processor to do the work of the bypassed processor. The processors may be arrayed in a pipeline.
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