US Patent No: 7,190,823

Number of patents in Portfolio can not be more than 2000

Overlay vernier pattern for measuring multi-layer overlay alignment accuracy and method for measuring the same

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ALSO PUBLISHED AS: 20030174879
ATTORNEY / AGENT: (SPONSORED)
 

Importance

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Abstract

An overlay vernier pattern for measuring multi-layer overlay alignment accuracy and a method for measuring the same is provided. A distance between a first alignment mark in a first material layer and a second alignment mark in an underlying second material layer is measured, so as to provide an alignment offset between the first material layer and the second material layer. In addition, a distance between the second alignment mark in the second material layer and a third alignment mark in a third material layer underlying the second material layer is measured, so as to provide an alignment offset between the second material layer and the third material layer. Because the second alignment marks can be repeatedly used, scribe line areas for forming these alignment marks and measuring time are saved to increase the production throughput.

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First Claim

Related Publications

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Patent Owner(s)

Patent OwnerAddressTotal Patents
UNITED MICROELECTRONICS CORP.HSINCHU4006

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Tzu-Ching Tai-Chung, TW 2 10

Cited Art

Patent Info (Count) # Cites Year
 
RENESAS ELECTRONICS CORPORATION (3)
6,118,517 Mask pattern for alignment 11 1997
6,801,313 Overlay mark, method of measuring overlay accuracy, method of making alignment and semiconductor device therewith 11 2000
6,849,957 Photomask including auxiliary mark area, semiconductor device and manufacturing method thereof 8 2000
 
ELPIDA MEMORY, INC. (2)
5,614,767 Alignment accuracy check pattern 23 1996
6,319,791 Semiconductor device manufacturing method and semiconductor device 12 1999
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (2)
6,362,491 Method of overlay measurement in both X and Y directions for photo stitch process 8 1999
6,309,944 Overlay matching method which eliminates alignment induced errors and optimizes lens matching 8 2000
 
FREESCALE SEMICONDUCTOR, INC. (1)
6,218,200 Multi-layer registration control for photolithography processes 23 2000
 
FUJITSU MICROELECTRONICS LIMITED (1)
5,005,046 Pattern forming method 11 1990
 
HITACHI, LTD. (1)
6,897,956 Apparatus and method for measuring alignment accuracy, as well as method and system for manufacturing semiconductor device 12 2002
 
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. (1)
5,635,336 Method for the preparation of a pattern overlay accuracy-measuring mark 14 1996
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
6,228,705 Overlay process for fabricating a semiconductor device 2 1999
 
KABUSHIKI KAISHA TOSHIBA (1)
5,917,205 Photolithographic alignment marks based on circuit pattern feature 16 1997
 
NEC CORPORATION (1)
5,322,593 Method for manufacturing polyimide multilayer wiring substrate 20 1992
 
NEC ELECTRONICS CORPORATION (1)
6,448,147 Semiconductor device and method for manufacturing the same 2 2001
 
OKI SEMICONDUCTOR CO., LTD. (1)
5,912,983 Overlay accuracy measuring method 40 1997
 
SANDIA CORPORATION (1)
5,783,340 Method for photolithographic definition of recessed features on a semiconductor wafer utilizing auto-focusing alignment 72 1997
 
SANSOCCA ALANDRO A.B., LLC (1)
6,172,409 Buffer grated structure for metrology mark and method for making the same 14 1997
 
SHARP KABUSHIKI KAISHA (1)
7,008,756 Method of fabricating an X/Y alignment vernier 2 2004
 
SHARP LABORATORIES OF AMERICA, INC. (1)
6,864,589 X/Y alignment vernier formed on a substrate 4 2001
 
UNITED MICROELECTRONICS CORP. (1)
5,866,447 Modified zero layer align method of twin well MOS fabrication 4 1996
 
VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION (1)
6,077,756 Overlay target pattern and algorithm for layer-to-layer overlay metrology for semiconductor processing 112 1998
 
XILINX, INC. (1)
6,716,653 Mask alignment structure for IC layers 6 2002

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
7,650,029 Multiple layer alignment sensing 0 2004
 
HYNIX SEMICONDUCTOR INC. (1)
7,595,258 Overlay vernier of semiconductor device and method of manufacturing the same 0 2007
 
SAMSUNG ELECTRONICS CO., LTD. (1)
7,602,072 Substrate having alignment marks and method of obtaining alignment information using the same 1 2007

Maintenance Fees

Fee Large entity fee small entity fee micro entity fee due date
7.5 Year Payment $3600.00 $1800.00 $900.00 Sep 13, 2014
11.5 Year Payment $7400.00 $3700.00 $1850.00 Sep 13, 2018
Fee Large entity fee small entity fee micro entity fee
Surcharge - 7.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge after expiration - Late payment is unavoidable $700.00 $350.00 $175.00
Surcharge after expiration - Late payment is unintentional $1,640.00 $820.00 $410.00