Configurable integrated circuit with offset connection
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United States of America Patent
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Mar 20, 2007
Grant Date -
N/A
app pub date -
Jun 30, 2004
filing date -
Jun 30, 2004
priority date (Note) -
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Abstract
Some embodiments of the invention provide an configurable integrated circuit ('IC'). This IC has at least fifty configurable nodes arranged in an array that several rows and columns. The IC also has several direct offset connections, where each particular direct offset connection connects two offset nodes that are neither in the same column nor in the same row in the array. In some embodiments, several direct connections do not include any intervening circuits. On the other hand, in some embodiments, several direct connections have intervening circuits, which differ from the nodes in the array.
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