Cross-point ferroelectric memory that reduces the effects of bit line to word line shorts
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United States of America Patent
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Mar 20, 2007
Grant Date -
Jan 5, 2006
app pub date -
Jul 1, 2004
filing date -
Jul 1, 2004
priority date (Note) -
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Abstract
A memory constructed from a dielectric layer sandwiched between a plurality of word conductors and a plurality of bit line conductors is disclosed. The dielectric layer includes a layer of ferroelectric material, and has first and second surfaces. The word conductors are located on the first surface. Each word conductor is connected to a corresponding word line driving circuit. The bit line conductors are located on the second surface. Each bit line conductor is connected to a corresponding bit line driving circuit and a corresponding sense amplifier by one or more disconnect switches. A disconnect switch is set to an open state if the bit line conductor connected to that disconnect switch is shorted to one of the word conductors.
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