Method and apparatus for processing data with a programmable gate array using fixed and programmable processors
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United States of America Patent
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Mar 20, 2007
Grant Date -
Jul 7, 2005
app pub date -
Feb 17, 2005
filing date -
Nov 19, 2001
priority date (Note) -
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Abstract
A method and apparatus for processing data within a programmable gate array comprise a first fixed logic processor and a second fixed logic processor that are embedded within the programmable gate array and detect a custom operation code. The processing continues when a fixed logic processor provides an indication of the custom operational code to the programmable gate array. The processing continues by having at least a portion of the programmable gate array, which is configured as a dedicated processor, performing a fixed logic routine upon receiving the indication from the fixed logic processor.
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