Automatic alignment of integrated circuit and design layout of integrated circuit to more accurately assess the impact of anomalies
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 20, 2007
Grant Date -
Sep 8, 2005
app pub date -
Mar 5, 2004
filing date -
Mar 5, 2004
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method, computer program product and system for assessing the impact of anomalies in a physical device. An anomaly may be detected in an integrated circuit. Upon detecting an anomaly, an image of the anomaly may be captured. A design layout of the image may be obtained. The image coordinates of the detected anomaly may be transformed into a common reference system, such as the design layout. By using a common unit of reference instead of different reference systems, automatic coordination of the integrated circuit and the design layout may have to be performed once instead of multiple times for multiple tools. The image coordinates of the detected anomaly may be transformed to the coordinates of a common reference system by vectorizing the image, matching polygons in both the image and the design layout and aligning the image of the anomaly with the design layout of the image.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully