Page buffer circuit with reduced size, and flash memory device having page buffer and program operation method thereof
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United States of America Patent
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Apr 3, 2007
Grant Date -
Jan 4, 2007
app pub date -
Nov 30, 2005
filing date -
May 25, 2005
priority date (Note) -
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Abstract
The present invention relates to a page buffer circuit with a reduced size, and a flash memory device having the page buffer circuit and program operation method thereof. According to the present invention, a page buffer circuit can perform a program operation of a Multi-Level Cell (MLC) using a data verify circuit even without a data compare circuit. Accordingly, an occupation area can be reduced and the size of a flash memory device can also be reduced.
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