Error-checking and correcting decryption-key memory for programmable logic devices
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United States of America Patent
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Apr 3, 2007
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N/A
app pub date -
May 17, 2002
filing date -
Mar 29, 2002
priority date (Note) -
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Abstract
Described are circuits that detect and correct for decryption key errors. In one example, a programmable logic device includes a decryption key memory with a number of decryption-key fields and, for each key field, an associated error-correction-code (ECC) field. The PLD additionally includes error-correction circuitry that receives each key and associated ECC and performs an error correction before conveying the resulting error-corrected key to a decryptor.
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