Low-voltage, multiple thin-gate oxide and low-resistance gate electrode
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United States of America Patent
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Apr 10, 2007
Grant Date -
Jun 22, 2006
app pub date -
Dec 22, 2004
filing date -
Dec 22, 2004
priority date (Note) -
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Abstract
A method of making a memory array and peripheral circuits together on a single substrate forms a dielectric layer, floating gate layer, inter-layer dielectric and mask layer across all regions of the substrate. Subsequently these layers are removed from the peripheral regions and dielectrics of different thicknesses are formed in the peripheral regions according to the voltages of the circuits in these regions. A conductive layer is formed over the memory array and the peripheral circuits to form control gates in the memory array and form gate electrodes in the peripheral regions.
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