Host to FPGA interface in an in-circuit emulation system
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United States of America Patent
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-
Apr 17, 2007
Grant Date -
N/A
app pub date -
Oct 10, 2001
filing date -
Oct 26, 2000
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A multi-purpose interface between a host computer and an FPGA. This interface uses an IEEE 1284 compliant EPP mode connection. When the host computer is initialized, a reset of the FPGA is carried out to clear the configuration memory of the FPGA. The data lines of the interface are then used to communicate unidirectional configuration data into the FPGA. The data are clocked by the host computer using the data strobe signal line to clock data into the FPGA. When the FPGA has been fully programmed, including programming an IEEE 1284 compliant EPP mode interface into the FPGA, the data lines are used for bidirectional communication between the host computer and the configured FPGA, in this embodiment operating as a virtual microcontroller.
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