Linking method under mother and child block architecture for building check area and logic page of the child block
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United States of America Patent
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Apr 17, 2007
Grant Date -
Jun 16, 2005
app pub date -
Dec 12, 2003
filing date -
Dec 12, 2003
priority date (Note) -
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Abstract
A method of reducing the frequency of erasing steps of a flash memory is described. A linking method under a mother and a child block architecture for building a check area and a logic page of the child block in order to reduce the frequency of erasing steps of the flash memory so that the service life of the flash memory can be extended and also the processing speed can be promoted.
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