Columnar 1T-N memory cell structure
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United States of America Patent
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Apr 24, 2007
Grant Date -
Jul 28, 2005
app pub date -
Aug 25, 2004
filing date -
Aug 8, 2002
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Abstract
A memory array architecture incorporates certain advantages from both cross-point and 1T-1Cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of memory cells, each column being provided in a respective stacked memory layer.
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