Memory device with clock multiplier circuit
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 24, 2007
Issued Date -
N/A
app pub date -
Mar 31, 2005
filing date -
Apr 24, 2001
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A memory device having a clock multiplier circuit. The memory device includes a clock generating circuit to receive a first clock signal having a first frequency and to generate a second clock signal having a second frequency that is a multiple of the first frequency. The memory device includes a data receive circuit to receive data at the frequency of the second clock signal and may also include a data transmit circuit to transmit data at the frequency of the second clock signal. Further, the clock generating circuit may additionally generate a third clock signal having a third frequency that is also a multiple of the first frequency, the third clock signal being supplied to a control circuit of the memory device to time the reception of control and/or address signals therein. In a particular embodiment the second frequency is a four-times or eight-times multiple of the first frequency, and the third frequency is a two-times multiple of the first frequency.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully