Method, system and memory controller utilizing adjustable write data delay settings
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United States of America Patent
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Apr 24, 2007
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app pub date -
Nov 15, 2005
filing date -
Apr 24, 2001
priority date (Note) -
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Abstract
A method, system and memory controller that uses adjustable write data delay settings. The memory controller includes control transmit circuitry, data transmit circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data transmit circuitry transmits data signals to the memory devices via respective data signal paths. The timing circuitry delays transmission of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective one of the memory devices.
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