Method and apparatus for test and repair of marginally functional SRAM cells
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 24, 2007
Grant Date -
Jun 23, 2005
app pub date -
Dec 2, 2003
filing date -
Dec 2, 2003
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of memory cells with a built-in self test. At least one weak memory cell is identified. The at least one weak memory cell is repaired. A second test stress is applied to the selected cells and the repaired cells with the built-in self test.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully