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Abstract

A ferroelectric memory including a bit line pair, a drive line parallel to and located between the bit lines, and an associated memory cell. The memory cell includes two capacitors, each capacitor connected to one of said bit lines via a transistor, and each capacitor is also connected to the drive line via a transistor. The gates of all three of the transistors are connected to a word line perpendicular to the bit lines and drive line, so that when the word line is not selected, the capacitors are completely isolated from any disturb. The bit lines may be complementary and the cell a one-bit cell, or the cell may be a two-bit cell. In the latter case, the memory includes a dummy cell identical to the above cell, in which the two dummy capacitors are complementary. A sense amplifier with three bit line inputs compares the cell bit line with a signal derived from the two dummy bit lines. The logic states of the dummy capacitors alternate in each cycle, preventing imprint and fatigue. The bit lines are partitioned into a plurality of second level bit lines, each connected to a top level bit line via a group select transistor. The memory includes a plurality of such cells, divided into groups, each group connected to one of the second level bit lines. The memory cells are read with a non-destructive read out method that differentiates between the different capacitances of a ferroelectric capacitor in different ferroelectric polarization states.

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First Claim