Method and apparatus for solving an optimization problem in an integrated circuit layout
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United States of America Patent
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May 8, 2007
Grant Date -
May 20, 2004
app pub date -
Dec 31, 2002
filing date -
Nov 18, 2002
priority date (Note) -
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Abstract
Some embodiments of the invention provide a method of solving an optimization problem. The problem includes a plurality of elements, and one or more solutions have been previously identified for each element. The method specifies a first solution set that has one identified solution for each element. In some embodiments, the method then iteratively examines all the elements of the problem. During the examination of each particular element, the method iteratively examines all the identified solutions for the particular element. During the examination of each particular solution, the method replaces the current solution for the particular element in the first solution set with a previously unexamined solution for the particular element if the replacement would improve the first set.
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