On-chip termination with calibrated driver strength
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United States of America Patent
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May 22, 2007
Grant Date -
N/A
app pub date -
Jan 20, 2005
filing date -
Jan 20, 2005
priority date (Note) -
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Abstract
Techniques are provided for controlling an on-chip termination resistance in an input or output (IO) buffer using calibration circuits. Each calibration circuit monitors the voltage between an external resistor and a group of on-chip transistors. When the effective resistance of the group of transistors matches the external resistance, the calibration circuit causes the effective resistance of drive transistors in the IO buffer to match the effective resistance of the group of on-chip transistors.
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