Method and apparatus for implementing frame header alterations using byte-wise arithmetic logic units
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United States of America Patent
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May 29, 2007
Grant Date -
Jan 1, 2004
app pub date -
Jun 27, 2002
filing date -
Jun 27, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and apparatus are provided for implementing frame header alterations using byte-wise arithmetic logic units (ALUs). First and second stage alteration engines include a plurality of first stage byte-wise arithmetic logic units (ALUs). Each ALU includes inputs for receiving frame data, command data, register data, and commands, and register data and data outputs. The first and second stage byte-wise ALUs respectively perform the received first and second stage commands and the second stage ALUs provide altered frame data output. The commands enable operations such as load, add, and, or, move, and the like used by the two-stages of byte-wise ALUs forming the alteration engines to perform the alterations or combine new header data into a stream of frame data.
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