Scalable DMA remapping on a computer bus
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United States of America Patent
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May 29, 2007
Grant Date -
Dec 7, 2006
app pub date -
Jun 1, 2005
filing date -
Jun 1, 2005
priority date (Note) -
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Abstract
A system for addressing bus components comprises a bus controller component that controls access between a CPU and a memory address space. A plurality of bus components connected to said bus controller over a bus are addressable via a memory mapped address within the address space. An address translation table is stored on at least one of the plurality of bus components. The bus translation table stores a translation between a virtual address and a real address.
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