Clock data recovery circuitry associated with programmable logic device circuitry
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United States of America Patent
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Jun 5, 2007
Grant Date -
Oct 25, 2001
app pub date -
Mar 13, 2001
filing date -
Mar 14, 2000
priority date (Note) -
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Abstract
A programmable logic device ('PLD') is augmented with programmable clock data recover ('CDR') circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling ('LVDS'). The circuitry may be part of a larger system.
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