Ultra low inductance multi layer ceramic capacitor
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 12, 2007
Grant Date -
Nov 24, 2005
app pub date -
Jul 19, 2005
filing date -
May 6, 2003
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A multilayer capacitor having a low parasitic inductance includes a first electrode, a second electrode, a dielectric, a first contact, and a second contact. The first electrode is substantially rectangular and it includes a first contact finger. The dielectric has a first surface and a second surface, wherein the first and second surfaces are situated opposite with each other. The first surface of the dielectric is coupled with the first electrode. The second electrode is substantially rectangular and it includes a first contact finger. The second electrode is coupled to the second surface of the dielectric. The first contact is coupled to the first contact finger of the first electrode. The second contact is coupled to the first contact finger of the second electrode. The second contact is situated at a minimal space from the first contact to reduce the parasitic inductance.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully