Importance

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Abstract

A flow bit mechanism and technique conveys per-channel flow control information pertaining to the status of output buffers located on line cards to at least one performance routing engine (PRE) of an intermediate network node, such as an aggregation router. Each line card generates a flow bit for each of its output buffers associated with an output channel. The state of the flow bit denotes a threshold reading on the depth of the output buffer, which is preferably organized as a first-in, first-out (FIFO) queue. The depth of the output queue is compared with a predetermined threshold value. If the depth of the FIFO is below the threshold, the state of the flow bit returned to the PRE indicates that more traffic can be accepted for that channel. If the depth of the FIFO is above the threshold, the state of the flow bit indicates that further traffic is denied for the channel until there is more space on the queue. The flow bit reflects the current state of the associated output queue rather than the change in state of that queue.

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First Claim