Programmable frequency divider
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United States of America Patent
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Jun 12, 2007
Grant Date -
Sep 14, 2006
app pub date -
Nov 29, 2005
filing date -
Nov 30, 2004
priority date (Note) -
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Abstract
A programmable frequency divider capable of operating in a normal mode and a fractional mode divides the input clock frequency by any integer `N` provided at the input. In the normal mode the input is divided by the integer `N`. The divided output signal has a 50% duty cycle if the input clock has a 50% duty cycle. In the fractional mode, fractional division can be achieved from dividing by 1.5 to dividing by 255.5 in steps of 0.5.
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