Advanced bandwidth allocation in PCI bus architecture

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United States of America Patent

PATENT NO 7231475
SERIAL NO

10768924

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Abstract

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A bus arbitration system and method allocates total bus bandwidth between latency sensitive and latency insensitive interfaces by utilizing windows to divide the total bandwidth into latency sensitive and latency insensitive portions. Each interface is initially allocated top-up numbers of latency sensitive and latency insensitive tokens to proportionally allocate bus accesses between the interfaces according to their requirements. For an interface having access to the bus, the number of tokens is decremented for each successful bus transfer.

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Patent Owner(s)

Patent OwnerAddress
CISCO TECHNOLOGY INC170 WEST TASMAN DRIVE SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Nakil, Harshad San Jose, CA 28 779
Reddy, Rajashekar Santa Clara, CA 24 1393
Singla, Ankur San Jose, CA 32 2321

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