Memory module, test system and method for testing one or a plurality of memory modules
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 12, 2007
Grant Date -
Dec 23, 2004
app pub date -
Jan 9, 2004
filing date -
Jan 11, 2003
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
The invention relates to an integrated memory module having a memory unit and a self-test circuit, the self-test circuit being embodied in such a way as to make available test data and test addresses for testing memory areas in the memory unit and to generate defect data depending on the detection of a defect, a test circuit being provided in order to receive defect data from one or a plurality of connectable memory modules to be detected, the test circuit being configured in such a way as to store the received defect data depending on addresses assigned thereto in the memory unit.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully