Importance

Loading Importance Indicators...

Abstract

A merged structure SRAM cell is provided that includes a first transistor and a second transistor. The second transistor gate forms a load resistor for the first transistor and the first transistor gate forms a load resistor for the second transistor. Also provided is a method of reading a memory cell that comprises applying a potential difference (V.sub.DIFF) to a selected memory cell by providing a column line potential (V.sub.C) and a row line potential (V.sub.R). According to this method, V.sub.DIFF is increased by an increment less than a transistor threshold voltage (V.sub.T). It is then determined whether the increased V.sub.DIFF results in a current flow on the column line for the selected memory cell. Also provided is a method of writing a memory cell that comprises applying V.sub.DIFF and increasing V.sub.DIFF by an increment more than V.sub.T to set the selected memory cell to a one state.

Loading the Abstract Image...

First Claim