Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
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United States of America Patent
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Jun 19, 2007
Grant Date -
Jul 4, 2002
app pub date -
Dec 28, 2000
filing date -
Dec 28, 2000
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Abstract
A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.
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