Memory module with testing logic
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United States of America Patent
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Jun 19, 2007
Grant Date -
Aug 25, 2005
app pub date -
Feb 4, 2004
filing date -
Feb 4, 2004
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A memory module that comprises a plurality of memory circuits, at least one serial presence detect (SPD) memory circuit, and a plurality of data lines that transfer data to and from the plurality of memory circuits. The memory module may further comprise a testing logic that utilizes data stored in the SPD memory circuit to inject a memory error into one or more of the plurality data lines.
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