Techniques for providing multiple termination impedance values to pins on an integrated circuit
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United States of America Patent
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Jul 3, 2007
Grant Date -
N/A
app pub date -
Mar 10, 2004
filing date -
Aug 29, 2001
priority date (Note) -
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Importance
Abstract
Techniques are provided for matching the characteristic impedance of different transmission lines coupled to I/O pins on an integrated circuit. On-chip termination impedance circuitry can generate different termination impedance values for each I/O pin. Each termination impedance value is selected to match the characteristic impedance of the transmission line coupled to a particular I/O pin. The termination impedance can be set in response to the value of an off-chip resistor. Bit shifter circuitry can change the termination impedance provided to individual I/O pins. The bit shifter circuitry can increase or decrease the termination impedance at any of the I/O pins without changing the value of the off-chip resistor.
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