Clock control circuit for test that facilitates an at speed structural test
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United States of America Patent
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Jul 3, 2007
Grant Date -
Aug 24, 2006
app pub date -
Feb 18, 2005
filing date -
Feb 18, 2005
priority date (Note) -
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Abstract
When testing an ASIC using functional clocks, a control circuit at the clock root incorporates additional test logic in the root and a deskewer for clock control, giving rise to a very flexible control that can pass clock signals at a number of clock rates and can pass only a single clock edge, thereby permitting the passage of the required number of clock pulses for a test. The system uses the functional clock and the clock distribution tree designed into the ASIC.
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