Deterministic addressing of nanoscale devices assembled at sublithographic pitches
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United States of America Patent
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Jul 10, 2007
Grant Date -
Jun 7, 2007
app pub date -
May 25, 2004
filing date -
Jun 2, 2003
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Abstract
A method for constructing and addressing a nanoscale memory with known addresses and for tolerating defects which may arise during manufacture or device operational lifetime. During construction, nanoscale wires with addresses are stochastically assembled. During a programming phase, nanoscale wires are stochastically selected using their stochastic addresses through microscale inputs and a desired address code is associated with the selected nanoscale wires. Memory addresses are associated to the codes and then selected using the known codes during read/write operations from/to the memory.
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