Test masks for lithographic and etch processes

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United States of America Patent

PATENT NO 7243316
APP PUB NO 20030229880A1
SERIAL NO

10321281

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Abstract

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A mask design is generated for patterning a test wafer using a lithographic or etch process, the process is characterized based on the patterned test wafer, and a pattern-dependent model is used based on the characterization to predict characteristics of integrated circuits that are to be fabricated by the lithographic or etch process.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC2655 SEELY AVENUE SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Smith, Taber H San Jose, CA 25 4092
White, David Cambridge, MA 206 7185

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