Parameter checking method for on-chip ESD protection circuit physical design layout verification
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United States of America Patent
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Jul 10, 2007
Grant Date -
Dec 2, 2004
app pub date -
May 30, 2003
filing date -
May 30, 2003
priority date (Note) -
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status (Latency Note)
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Abstract
A checking mechanism for complete full-chip ESD protection circuit design and layout verification at layout level identifies all of both intentional and parasitic ESD devices contained in the design layout file and compiles a netlist. The checking mechanism then determines the critical operating parameters of the identified ESD devices and determines if the parasitic devices will negatively effect ESD protection performance. The checking mechanism then determines if the intentional devices meet design specifications; eliminates parasitic devices which will not negatively effect ESD protection from the netlist, and retains those parasitic devices which may lead to ESD protection malfunction. Design layout verification and faults are then reported.
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