Memory module and method having improved signal routing topology
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United States of America Patent
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Aug 30, 2005
Grant Date -
Dec 16, 2004
app pub date -
Jun 11, 2003
filing date -
Jun 11, 2003
priority date (Note) -
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status (Latency Note)
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Abstract
A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.
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