Dual processor framer
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United States of America Patent
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Jul 17, 2007
Grant Date -
N/A
app pub date -
May 17, 2002
filing date -
May 17, 2001
priority date (Note) -
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Abstract
A dual processor framer includes a receiver and a transmitter which share common circuitry and/or code. Separate direct memory access controllers may be used for each of the receiver and transmitter. Processing is distributed over two or more processors. One processor may be a lower power processor while another processor may be a higher power processor. At least one of the two or more processors may be programmable or reconfigurable. The transceiver is configured to provide internal loop back self testing at various points in the processing. Timing within the transceiver may be established almost entirely by a single clock domain.
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