Dual link DVI transmitter serviced by single phase locked loop
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United States of America Patent
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Aug 7, 2007
Grant Date -
Jan 4, 2007
app pub date -
Sep 5, 2006
filing date -
Feb 12, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
A dual link transmitter constructed according to the present invention employs a single Phase Locked Loop (PLL) to service both a primary link and a secondary link during dual link mode operations. The structure of the dual link transmitter includes both a primary link PLL and a secondary link PLL. The primary link PLL produces a primary link clock and the secondary link PLL produces a secondary link clock. During dual single link operations, the primary link clock is used to service the primary link while the secondary link clock is used to service the secondary link. However, during dual link operations, the primary link clock is used to service both the primary link and the secondary link.
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