Ternary CAM with software programmable cache policies
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United States of America Patent
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Aug 14, 2007
Grant Date -
Jun 1, 2006
app pub date -
Jan 5, 2006
filing date -
Apr 28, 2003
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A circuit comprising a plurality of first line buffers, an arbiter and a cache. The plurality of first line buffers may be configured to communicate on a plurality of first busses. The arbiter may be configured to perform an arbitration among the first line buffers. The cache block may be configured to (i) determine a particular policy of a plurality of policies in response to a first transaction request from one of the first line buffers winning the arbitration and (ii) generate a second transaction request based upon the first transaction request and the particular policy.
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