SEU and SEFI fault tolerant computer
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United States of America Patent
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Aug 21, 2007
Grant Date -
Jan 6, 2005
app pub date -
Jan 28, 2004
filing date -
Jan 28, 2003
priority date (Note) -
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Abstract
A non-hardened processor is made fault tolerant to SEUs and SEFIs. A processor is provided utilizing time redundancy to detect and respond to SEUs. Comparison circuitry is provided in a radiation hardened module to provide special redundancy with the need to run additional processors. Additionally, a hardened SEFI circuit is provided to periodically send a signal to the process which, in the case of a processor not in the SEFI state, initiates production by the processor of a 'correct' response. If the correct response is not received within a particular time window, the SEFI circuit initiates progressively severe actions until a reset is achieved.
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