Method and apparatus for an efficient memory built-in self test architecture for high performance microprocessors
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United States of America Patent
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Aug 21, 2007
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app pub date -
Jun 16, 2004
filing date -
Jun 16, 2004
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Abstract
A memory BIST architecture provides an efficient communication interface between external agents, e.g., external tester and a memory BIST module. The memory BIST architecture reduces diagnostics efforts by dividing the search space and allowing the test and debug to be concentrated on the failing memory. The memory BIST architecture is divided into two levels, a memory BIST sequencer level and a satellite memory BIST module. The memory BIST sequencer level includes a set of registers that provide an interface between external agents attempting to communicate with the MBIST module and the Satellite MBIST module.
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