Importance

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Abstract

A logic circuit is provided that implements soft error detection and recovery for protecting the logic circuit from the negative effects of soft errors caused by single event upsets. The logic circuit may include a configurable processing module, an input buffer, an output buffer, a configuration and scrub control module and a buffer control module. The configuration memory of the configurable processing element may be periodically read and checked for errors. If an error is detected, the configurable processing element may be at least partially reloaded, the output data produced since the last checking operation is discarded, and the input data may be reprocessed by the reloaded processing element. If no error is detected, then the output data may be marked for release and processing continues. Additionally, the logic circuit may include error checking of the input buffer, the output buffer and control logic to ensure that the logic circuit has complete soft error detection and recovery capability.

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First Claim