Method for manufacturing wafer level chip scale package using redistribution substrate
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United States of America Patent
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Sep 4, 2007
Grant Date -
Apr 13, 2006
app pub date -
Oct 7, 2005
filing date -
Oct 8, 2004
priority date (Note) -
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Abstract
The present invention provides a method for manufacturing a wafer level chip scale package using a redistribution substrate, which has patterned bump pairs connected by redistribution lines and formed on a transparent insulating substrate. The redistribution substrate is produced separately from a wafer and then bonded to the wafer. One part of each bump pair is in contact with a chip pad on the active surface of the wafer, and the other part coincides with one of holes formed in the wafer. Conductive lines are formed in the holes and on the non-active surface of the wafer. External connection terminals are formed on the conductive lines at the non-active surface.
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