Open loop bandwidth test architecture and method for phase locked loop (PLL)
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United States of America Patent
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Sep 4, 2007
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N/A
app pub date -
May 19, 2005
filing date -
Jun 14, 2004
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Abstract
A phase locked loop (PLL) can include a test loop filter (100) that generates a control voltage (V.sub.CTRL) for input to a voltage controlled oscillator (VCO). In a test mode, a control voltage can be varied and resulting output frequencies recorded, from which an open loop bandwidth can be determined. A control voltage can be varied by enabling a switch element (104-1) that can provide a current path through load resistance (RL) of test loop filter (100). Current provided to the test loop filter can be varied according to test signals to provide a variable control voltage (V.sub.CTRL).
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