Memory rank decoder for a multi-rank Dual Inline Memory Module (DIMM)
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United States of America Patent
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Sep 4, 2007
Grant Date -
Jun 15, 2006
app pub date -
Dec 10, 2004
filing date -
Dec 10, 2004
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Abstract
The invention refers to a Memory Rank Decoder for a Multi-Rank Dual Inline Memory Module (DIMM) having a predetermined number of DRAM memory chips mounted on a printer circuit board (PCB), wherein each DRAM memory chip comprises a predetermined number of stacked DRAM memory dies which are selectable by a memory rank selection signal (r), wherein the memory rank decoder generates the memory rank selection signal (r) in response to external selection signals applied to the dual inline module (DIMM).
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