Memory stacking system and method
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United States of America Patent
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Sep 11, 2007
Grant Date -
Sep 7, 2006
app pub date -
Apr 28, 2006
filing date -
Sep 1, 2004
priority date (Note) -
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Abstract
A method of forming a stacked memory module from a plurality of memory devices is provided. Each of the plurality of memory devices is modified to include a logic block for decoding a plurality of chip select signals. A first high density memory module is also provided that includes the modified memory devices and a serial presence detect device. The first high density memory module is included within an electronic system. Also, an additional method of forming a stacked memory module is provided, the method requiring modification of an address buffer to include a logic block for decoding a plurality of chip select signals. A second high density memory module is also provided that includes the modified address buffer and a serial presence detect device. The second high density memory module is included within an electronic system.
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