Non-volatile memory and method with bit line to bit line coupled compensation
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United States of America Patent
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Sep 11, 2007
Grant Date -
Oct 12, 2006
app pub date -
Jun 2, 2006
filing date -
Sep 17, 2003
priority date (Note) -
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Abstract
When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.
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